(A) Field of the Invention
The present invention is related to a spilling method in register files for a microprocessor, and more particularly, to a spilling method in register files applied to a Parallel Architecture Core (PAC) processor.
(B) Description of the Related Art
Nowadays, digital signal processors (DSP) are widely used for apparatuses that need a large amount of computation such as mobile apparatuses. As the development of communication technology focuses on high performance and low power consumption, DSPs with large communication source, limited information paths and register storage capability have been developed. The DSP computation sources are divided into plural clusters that are associated with specific local register files to reduce hardware complexity.
Registers have the function of storing data and need to be efficiently used for achieving high performance during operation. The selection of language device to allocate the instruction to the register and the processing of moving the data using the language device are called “register allocation.” The register allocation is crucial to the complier's performance. Improper allocation will degrade the script code size and operation time performance.
Pages 47 to 57, Vol. 6 of “Computer Languages,” written by Chaitin et al. and U.S. Pat. No. 4,571,678 entitled “Register Allocation and Spilling via Graph Coloring” show register allocation using graph coloring, in which program instruction from the definition to the output is the so-called live range, and the corresponding registers are assigned different colors for the overlap portion of the live range. Different colors indicate different registers.
When the number of registers is insufficient to store the live range of the program instruction, “spilling” occurs. Traditionally, the live range is changed to be stored in an external memory when spilling occurs. However, storage in the external memory has high communication cost, and causes decreased processor performance.